Structure and method for bonding to copper interconnect structures

ABSTRACT

An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.

[0001] This patent application claims the benefit of the provisionalpatent application filed on Dec. 20, 2002, and assigned application Ser.No. 60/435,033.

BACKGROUND OF THE INVENTION

[0002] Integrated circuits (or chips) comprise a silicon substrate andsemiconductor devices, such as transistors, formed from doped regionswithin the substrate. A conductive interconnect system overlying thesubstrate electrically connects the doped regions to form electricalcircuits.

[0003] A conventional interconnect system comprises a plurality ofsubstantially vertical conductive vias or plugs interconnecting one ormore substantially horizontal conductive layers (each horizontal layerreferred to as an “M” or metallization layer), with a dielectric layerdisposed between two vertically adjacent conductive layers. A typicalinterconnect system comprises 6-9 horizontal conductive layers, eachfurther comprising a plurality of conductive lines or traces. Conductivevias in the first or lowest interconnect level connect underlyingsemiconductor device regions to overlying conductive layers. Upper levelconductive vias interconnect two vertically adjacent conductive layers.The conductive vias and the conductive lines are formed by employingconventional techniques, including metal deposition, photolithographicmasking, patterning and subtractive etching. Most integrated circuitsemploy tungsten conductive vias and aluminum conductive layers.

[0004] After fabrication, the integrated circuit is enclosed in apackage comprising a plurality of externally-disposed pins or otherconductive elements for connecting the packaged chip to electroniccomponents in an electronic device. To connect the integrated circuit todie package pins, an uppermost conductive layer of the chip interconnectsystem comprises a plurality of conductive bond pads (referred to as thebond pad layer) for receiving a conductive element (e.g., a bond wire,solder bump or solder ball) that connects the integrated circuit to thepackage pins. In an aluminum-based interconnect system, the topmostaluminum layer is masked, patterned, and etched to define the aluminumbond pads therein.

[0005]FIG. 1 illustrates a device package 100 comprising package leads102. An integrated circuit 104 is affixed within a die attach area 106.Bond pads 110 (in one embodiment formed from aluminum) disposed on anupper surface 112 of the integrated circuit 104 are connected to thepackage leads 102 by gold (or gold alloy) wires 114. Generally, the bondpads 110 vary between about 40-80 microns and 50-150 microns in lengthand width, respectively. Although square bond pads as illustrated arecommon, use of rectangular bond pads is also known in the prior art. Theprocess of electrically connecting the bond pads 110 to the packageleads 102 is referred to as wire bonding.

[0006] In another known package structure, referred to as flip-chip orbump bonding, the interconnecting bond wires are replaced with depositedsolder bumps 120 formed on the bond pads 110 of an integrated circuit121. See FIG. 2. Conventionally, an under-bump metallization layer (notshown) is formed intermediate the solder bumps 120 and the bond pads110. Connection to a package 122 of FIG. 3 is accomplished by invertingthe integrated circuit 121 and soldering the bumps 120 to receiving pads124 on the package 122. The receiving pads 124 are in conductivecommunication with a corresponding package lead. In the example of FIG.3 the package leads comprise an array of balls 126 in the form of a ballgrid array. Thus integrated circuits formed with an aluminuminterconnect system and aluminum bond pads 110 can be packaged usingeither the wire bond or bump bond process.

[0007] As integrated circuit devices and interconnect systems arereduced in size and made to carry higher frequency analog signals andhigher data-rate digital signals, aluminum interconnect structures canimpose unacceptable signal propagation delays within the chip. Also, asvia openings continue to shrink it becomes increasingly difficult todeposit conductive material in the smaller openings.

[0008] Given these known disadvantages of aluminum interconnectstructures, copper (and its alloys) is becoming the interconnectmaterial of choice. Copper is a better conductor than aluminum (with aresistivity of 1.7 to 2.0 micro-ohm-cm compared to 2.7 to 3.1micro-ohm-cm for aluminum), is less susceptible to electromigration (aphenomenon whereby an aluminum interconnect line thins and caneventually separate due to the electric field and thermal gradientsformed by current flow through the line), and can be deposited at lowertemperatures (thereby avoiding deleterious effects from high thermalbudgets) and in smaller openings. The lower resistance of copper reducessignal propagation time. Moreover, recent advances in electroplating andelectrodeposition make the process of depositing copper quiteeconomical.

[0009] A dual damascene process, one preferred technique for forming acopper interconnect system, integrally forms both the conductivevertical via portion and the conductive horizontal interconnect portionof a copper metallization layer. A via is formed in a dielectric layer,followed by formation of an overlying horizontal trench. A metaldeposition step simultaneously fills both the via and the trench,forming a complete metal interconnect layer comprising a substantiallyvertical conductive via and a substantially horizontal conductiverunner. A chemical/mechanical-polishing step planarizes the dielectricsurface by removing copper deposits formed on the surface during thecopper deposition step.

[0010] An example of a prior art damascene structure is illustrated inthe cross-sectional view of FIG. 4, comprising a dielectric layer 138deposited or formed on a lower level interconnect structure 139. Anopening formed in the dielectric layer 138 is filled with a suitableconductive material 140, such as copper, to form a conductive trench 142and a conductive via 144 in contact with the lower level interconnectstructure 139. The topmost metallization layer is used to fabricatecopper bond pads as is well known in the art.

[0011] Although attempts have been made to wire bond to copper bondpads, these efforts remain an academic exercise and have not beenimplemented in commercial fabrication processes. Instead, the industryemploys the flip-chip solder bump method for connecting copper bond padsto flip-chip package leads. However, if it is desired to use a wire bondpackage for an integrated circuit having a copper interconnect system,aluminum bond pads are fabricated over and in conductive communicationwith the copper interconnect structures. Bond wires can be bonded to thealuminum bond pads. Alternatively, a solder bump can be bonded to thealuminum bond pad for use with a flip chip package.

[0012] In the integrated circuit fabrication industry, a significantfraction of fabricated chips are shipped to a separate facility forpackaging or preparing the wafers for subsequent assembly, according tothe wire bonding or the flip-chip techniques described above. Thefacility is generally operated by a third-party contractor.Transportation of wafers from the manufacturing site to the packagingfacility may take a few days to several weeks. Depending on marketconditions and demand, the wafers may then be stored in inventory,typically for a few months, before packaging.

[0013] It is known that copper forms an oxide and corrodes when exposedto an ambient atmosphere. Thus during shipment and storage at thepackaging facility, exposed copper pads will oxidize. The coppercorrosion process is not self-limiting (i.e., the corrosion andoxidation continue indefinitely) and forms a complex array of oxides onthe copper surface. The longer the exposure duration, the greater thepropensity for an exposed copper pad to undergo such chemical changes.Since the copper oxide continues to grow without limit, the oxide depthis unknown and any cleaning process employed to remove the copper oxidemay not remove all of the oxide.

[0014] To prevent oxide formation on the copper bond pads, prior toshipping the wafer to the packaging facility a semiconductormanufacturer forms an aluminum alloy layer (e.g., aluminum-copper,aluminum-silicon-copper) overlying the copper pad. The aluminum promotesformation of the self-passivating aluminum-oxide layer described aboveand substantially limits copper oxide formation. However, forming thealuminum layer adds two mask steps to the fabrication process. It isknown that each mask layer can increase wafer cost and fabrication cycletime and lower the process yield. Thus semiconductor manufacturers seekto limit mask steps. If the semiconductor manufacturer elects not toform an aluminum layer over the copper bond pads, it will be necessaryto form the aluminum layer prior to the bumping step for forming solderbumps. This would require cleaning of the copper oxide prior topackaging.

[0015] To summarize, according to the prior art, integrated circuitsformed with an aluminum interconnect system and aluminum bond pads canbe packaged using either the wire bond or bump bond process. Onlyminimal cleaning of the aluminum surface is required prior to packaging.For a copper interconnect system, the semiconductor fabricator candeposit an aluminum layer over the copper bond pads to limit copperoxide formation during shipping and storage prior to packaging, at theexpense of two additional mask steps. With the aluminum layer in place,either wire bonding or flip chip packaging can be employed. According toanother process, the fabricator ships the integrated circuits withexposed copper bond pads, necessitating a cleaning step prior to bumpingand subsequent packaging. After cleaning, bump bonds are formed and theintegrated circuit packaged in a bump bond package.

[0016] Beginning in FIG. 5, there is illustrated one prior art processfor forming an aluminum layer and solder bumps for a copper interconnectstructure, including the aforementioned copper oxide cleaning step. Acopper bond pad 200 is formed within a trench or opening of a substrate201 as shown. As described above, the substrate 201 comprises multiplealternating layers of dielectric and interconnects overlying asemiconductor substrate comprising doped regions.

[0017] A passivation stack 202 (typically a stack of dielectric materiallayers comprising silicon dioxide and/or silicon nitride) is formed overthe bond pad 200. A photoresist layer (not shown in FIG. 5) isdeposited, masked, patterned and developed to create an opening therein.An opening 204 is then formed in the passivation stack 202 according tothe pattern in the photoresist layer. See FIG. 6.

[0018] Copper oxide on a surface 206 of the copper pad 200 is removedduring a sputter clean process (also referred to as a back sputterprocess) wherein energetic argon ions (produced in a radio-frequencyback sputter tool) represented by arrowheads 208 in FIG. 6, impinge uponthe copper pad 200 through the opening 204.

[0019] An aluminum layer is deposited and etched according to a maskpattern (not shown), forming an aluminum pad 212 as illustrated in FIG.7. This step represents a first one of the two required additional masklayers referred to above. At the interface between the copper pad 200and the aluminum pad 212, intermetallic compounds can be formed as metalatoms of one material diffuse into the other material. Suchintermetallic compounds may be brittle and susceptible to cracking,causing irregularities in the interface conductivity and degradingdevice performance. To avoid the formation of the intermetallic layer, abarrier layer (not shown in FIG. 7) is formed between the aluminum pad212 and the copper pad 200. Exemplary materials comprising the barrierlayer include: tantalum, tantalum-nitride and titanium nitride.

[0020] A passivation layer 214 (see FIG. 8) is formed and patterned,defining an opening 216 according to a patterned photoresist layer (notshown in FIG. 8). This photoresist step represents a second of the tworequired additional mask layers.

[0021] Hence, either the semiconductor fabrication facility or thebumping house forms aluminum pads over the copper bond pads, asdescribed above. The wafer is delivered for solder bump formation withexposed aluminum pads. The first process performed in a bump-bondingpackaging operation is cleaning of the aluminum pad 212. In thiscleaning step argon ions, represented by arrowheads 217 in FIG. 8, areproduced in a radio-frequency (RF) back-sputtering tool and impinge uponthe aluminum pad 212 to reduce any aluminum oxide formed thereon. Thisoxide removal step is typically carried out in the same sputterdeposition tool where the under-bump metallization (UBM) material isdeposited, as described below.

[0022] Prior to formation of the UBM layer, sometimes the bumping houseprefers to deposit an additional aluminum layer on the aluminum pad 212to present a clean surface for the UBM layer. Another mask step isrequired to form this aluminum layer, thus increasing the cost andprocess cycle time.

[0023] An under-bump metallization layer 218 (see FIG. 9) is formed andpatterned according to a mask layer pattern not shown in FIG. 9.Exemplary compounds for the UBM layer 218 comprise:titanium-nickel-vanadium or copper-chromium-nickel. A solder bump 220 isformed by conventional techniques overlying the under-bond metallizationlayer 218 as shown in FIG. 10.

[0024] In a wire bonding process, the under-bump metallization layer isnot required. Instead, a wire bond is formed on the aluminum pad 212 toconnect the integrated circuit to the package.

[0025] It is known that the conventional RF back-sputtering process (asdescribed above in conjunction with the FIG. 6) for removing oxide (andother surface films) from the copper pad 200 can cause significantdamage to the integrated circuit and the copper film surface. Thisdamage results from the energy imparted to the surface by the energeticargon ions represented by the arrowheads 208 in FIG. 6. The surface ofthe copper bond pad 200 may be significantly roughened, making itdifficult for the subsequent aluminum layer 212 to nucleate and growadequately on the pad 200. Therefore, the device performance may bedegraded when the RF back-sputtering process is used to clean theoxidized copper surface. In the worst case, wafer plasma damage canoccur, rendering the device useless.

BRIEF SUMMARY OF THE INVENTION

[0026] The present invention comprises a method for forming a solderbond on a copper surface, comprising forming the copper surface, whereinunwanted copper oxide forms on the copper surface. The copper surface isreduced the copper oxide and the solder bond formed on the reducedcopper surface.

[0027] The invention further comprises a solder bond structurecomprising a substrate and a hydrogen-reduced copper pad overlying thesubstrate. A passivation layer having an opening defined thereinoverlies the copper pad. An under-bump metallization layer is disposedwithin the opening and the solder bond structure is disposed overlyingthe under-bump metallization layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention can be more easily understood and theadvantages and uses thereof more readily apparent, when considered inview of the following detailed description when read in conjunction withthe following figures wherein:

[0029]FIG. 1 is a perspective cut-away view of a wire bond package foran integrated circuit.

[0030]FIGS. 2 and 3 illustrate a flip-chip integrated circuit devicestructure.

[0031]FIG. 4 is a cross-sectional view illustrating a dual damasceneinterconnect structure.

[0032]FIGS. 5-10 are cross-sectional views taken along a common planeillustrating sequential processing steps in the fabrication of a priorart solder bump structure.

[0033]FIGS. 11-14 are cross-sectional views taken along a common planeillustrating sequential processing steps in the fabrication of a solderbump according to one embodiment of the present invention.

[0034]FIG. 15 is a cross-sectional view of an aluminum layer formed overa copper bond pad.

[0035]FIGS. 16 and 17 are cross-sectional views taken along a commonplane illustrating sequential processing steps in the fabrication of asolder bump according to a second embodiment of the present invention.

[0036] In accordance with common practice, the various described devicefeatures are not drawn to scale, but are drawn to emphasize specificfeatures relevant to the invention. Reference characters denote likeelements throughout the figures and text.

DETAILED DESCRIPTION OF THE INVENTION

[0037] Before describing in detail the particular copper oxide cleaningprocess and a structure so formed in accordance with the presentinvention, it should be observed that the present invention residesprimarily in a novel and non-obvious combination of elements and methodsteps. Accordingly, these elements and steps have been represented byconventional elements and steps in the drawings, showing only thosespecific details that are pertinent to the present invention so as notto obscure the description with structural details that will be readilyapparent to those skilled in the art having the benefit of thedescription herein.

[0038] According to the teachings of the present invention, the priorart step of RF back-sputtering is replaced with a cleaning method thatemploys a reducing atmosphere to remove oxidation from a copper bond padof an integrated circuit. In one embodiment the reducing atmospherecomprises a plasma containing hydrogen (H₂) or ammonia (NH₃) (or anotherhydrogen-containing species). The proposed cleaning step can be carriedout in the conventional RF back sputtering chamber, with minor hardwaremodifications, at very small additional cost, thus eliminating the needto purchase new equipment. The teachings of the invention are alsoapplicable to the removal of oxides from other surfaces. In oneembodiment the reducing process of the present invention is employedprior to formation of a UBM layer over which a solder bump is formed forbump bonding the integrated circuit to a package.

[0039] Because the process of the present invention relies on chemicalreduction to remove the copper oxide, rather than bombardment of theoxide by energetic ions as disclosed in the prior art, bond pad damageis significantly reduced when compared with the prior art bombardmentprocess. Moreover, there is reduced roughening of the pad surface and alower interfacial resistance between the cleaned copper pad and the UBMlayer formed thereover (or any layer formed over a metallic pad cleanedaccording to the present invention), both features promoting improvedcircuit performance.

[0040] According to the prior art process, as the energetic ions bombardthe copper pad surface to remove the oxide, copper is also sputteredfrom the surface. The sputtered copper re-deposits back on the wafer,developing current leakage paths on the surface of the dielectricmaterial in which the copper bond pad is formed. This phenomenon issubstantially reduced according to the present invention as littlecopper is sputtered from the surface during the novel cleaning process.These and other advantages offered by the present invention improve thereliability of an integrated circuit cleaned according to the teachingsof the present invention. Also, according to the present invention, twomask layers in the prior art process are avoided and one metaldeposition step (formation of the aluminum pad overlying the copper pad)is eliminated.

[0041] According to one embodiment of the invention, an inert carriergas, such as argon (Ar) or nitrogen (N₂) is used in a relatively smallquantity, i.e., a sufficient quantity to strike a plasma in the chamber.Once the plasma stabilizes, the inert gas flow can be terminated. Apreferred embodiment uses a flow rate ratio of the hydrogen-containingspecies to the carrier gas of about 1:1 to 10:1, preferably about 2:1.

[0042] An exemplary reduction reaction of the copper-oxide by thehydrogen-containing species is described by the following equations:

[0043] (a) An ionization step to form reactive H⁺ ions fromhydrogen-containing gas in plasma in a conventional RF back-sputterchamber. For example, if the hydrogen containing species is molecularhydrogen, the reaction is:

H₂=2H⁺  (1)

[0044] (b) A reduction of the oxide on top of copper pad by the H⁺ ions:

Cu_(x)O+2H⁺=Cu+H₂O  (2)

[0045] The present invention further comprises an in-line method fordetermining the process end-point by measuring the surface reflectivityof the copper bond pad both before and after the copper oxide reductionstep. An oxidized copper film is about 40% to 80% less reflective than afilm that has undergone the cleaning steps of the present invention. Afreshly reduced copper oxide film according to the process of thepresent invention, exhibits film reflectivity that is similar to thereflectivity of freshly deposited copper, i.e., deposited usingconventional sputter deposition techniques.

[0046] The structure and method of the present invention, as applied tobump bonding of an integrated circuit to a bumped package, isillustrated in FIGS. 11-14. As illustrated in FIG. 11, the copper bondpad 200 is formed within the substrate 201. As described above, the bondpad 200 provides an interconnection region between the devices of theintegrated circuit and a conductive terminal of a package, such as thepackage 100 of FIG. 1 or the package 122 of FIG. 4A. The bond pad 200can be formed according to known damascene or dual damascene techniqueswithin a previously-formed via opening and/or trench in the substrate201. Typically the bond pad 200 is formed by electrodepositing copper asexplained above. Exemplary materials of the substrate 201 comprise,silicon dioxide-based materials, organo-silicate materials, silicates,fluorine-based dielectrics, low-dielectric constant materials such asxerogels, areogels and spin-on dielectrics, and combinations ormulti-layers thereof.

[0047] As illustrated in FIG. 12, a passivation layer 240 is formedoverlying the bond pad 200 and patterned according to an opening in anoverlying photoresist layer, not shown in FIG. 12, to form an opening242 above the bond pad 200. Material of the passivation layer comprisessilicon carbide, silicon nitride, silicon dioxide or combinationsthereof, or any suitable material that can serve as a passivation layer.

[0048] An arrowhead 250 in FIG. 12 represent ions of ahydrogen-containing species contacting the copper pad 200, reducing thecopper oxide according to equation (2) above. The reduction reaction canbe performed, for example, in the same tool used to deposit the UBMlayer according to the next step. Hydrogen is introduced into thechamber and ionized by the chamber plasma.

[0049] In FIG. 13, an under-bump metallization (UBM) layer 252 isformed. In one embodiment, a material of the UBM 252 may include knownmaterials to prevent intermixing of copper in the copper pad 200 with amaterial from which the solder bump 220 (see FIG. 14) is formed.Candidate UBM layer materials comprise multilayer structures thatinclude: copper and chromium, nickel-based materials, refractory metalsand compounds of titanium, tantalum, molybdenum and tungsten.

[0050] A reflow solder bump 220 is formed according to known methods onthe copper pad 200, see FIG. 14. The solder bump 220 compriseslead-based or lead-free materials.

[0051] Although the present invention is executed without a sputteringcomponent in the cleaning process, in another embodiment it may beadvisable to include sputtering particles during the reduction processto, for example, remove any deposits from an upper surface of thepassivation layer 240. Additional argon or nitrogen molecules can beadded to provide the sputtering component.

[0052] The teachings of the present invention have been described asapplied to the formation of solder bump on a copper bond pad. Theteachings can also be applied to the formation of any structure on acopper pad wherein it is first necessary to remove oxides from thecopper pad surface. For example, the cleaning process of the presentinvention can be used to clean the copper surface prior to the formationof an aluminum pad thereon for wire bonding the integrated circuit to awire-bond type package. See FIG. 15 wherein an aluminum layer 258 isformed over the copper pad 200 that has been previously cleanedaccording to the teachings of the present invention. The cleaningprocess of the present invention can also be applied to any metalsurface over which it is desired to form a solder bond surface, i.e., asurface that will adhere to a solder material.

[0053] In yet another embodiment, illustrated in FIGS. 16 and 17, aninterconnect structure 260 (for example, a power bus of an integratedcircuit) is connected to the copper bond pad 200 through a plurality ofvias 262 that provide electrical conductivity between the interconnectstructure 260 and the bond pad 200. It is known that current crowdingcan occur in the regions 264 where the under-bump metallization layer252 contacts the copper bond pad 200. The higher current flow in theseregions 264 causes a material temperature increase, possibly leading tostructural damage. The plurality of vias 262 provide multiple currentpaths to spread the current flow, reducing current crowding effects.Additionally, the plurality of vias 262 provide mechanical support forthe bond pad 200, especially during a wire bonding process whendownwardly directed forces are applied to any structure (such as analuminum pad or solder bump) over the pad 200 during packaging andassembly.

[0054] While the invention has been described with reference topreferred embodiments, it will be understood by those skilled in the artthat various changes may be made and equivalent elements may besubstituted for elements thereof without departing from the scope of thepresent invention. The scope of the present invention further includesany combination of the elements from the various embodiments set forthherein. In addition, modifications may be made to adapt a particularsituation to the teachings of the present invention without departingfrom its essential scope thereof Therefore, it is intended that theinvention not be limited to the particular embodiment disclosed as thebest mode contemplated for carrying out this invention, but that theinvention will include all embodiments falling within the scope of theappended claims.

What is claimed is:
 1. A method for forming a solder bond on a copperpad, comprising: forming the copper pad; forming a passivation layerover the copper pad; forming an opening in the passivation layer toexpose a surface of the copper pad; reducing copper oxide on thesurface; and forming the solder bond on the reduced surface.
 2. Themethod of claim 1 wherein the step of forming the solder bond furthercomprises forming an under-bump metallization layer on the reducedsurface.
 3. The method of claim 2 further comprising forming a solderbump on the under-bump metallization layer.
 4. The method of claim 1wherein the step of forming the solder bond further comprises forming analuminum layer on the reduced surface.
 5. The method of claim 1 whereinthe reducing step further comprises forming hydrogen ions and subjectingthe exposed copper pad surface to the hydrogen ions.
 6. The method ofclaim 5 wherein the step of forming hydrogen ions and subjecting theexposed copper pad surface to the hydrogen ions is carried out in aradio-frequency back sputter chamber.
 7. The method of claim 5 whereinthe step of forming hydrogen ions further comprises subjecting ahydrogen containing species to a plasma for forming the hydrogen ionsfrom the hydrogen containing species.
 8. The method of claim 1 whereinthe copper pad is formed in a semiconductor substrate.
 9. The method ofclaim 8 wherein the semiconductor substrate comprises interconnectstructures, and wherein the copper pad is in conductive communicationwith at least one of the interconnect structures.
 10. The method ofclaim 1 further comprising; determining a first surface reflectivity ofthe copper pad surface prior to the reducing step; determining a secondsurface reflectivity of the copper pad surface following the reducingstep; and controlling the reducing step according to the first and thesecond surface reflectivity.
 11. The method of claim 1 furthercomprising sputtering particles on the passivation layer and thesurface.
 12. The method of claim 11 wherein the step of sputteringparticles further comprises sputtering argon ions.
 13. The method ofclaims 1 wherein the copper pad is formed on an integrated circuit. 14.A method for forming a solder bond on a copper surface, comprisingforming the copper surface, wherein unwanted copper oxide forms on thecopper surface; reducing the copper oxide; and forming the solder bondon the reduced copper surface.
 15. The method of claim 14 wherein thereducing step further comprises exposing the copper surface to hydrogenspecies ions.
 16. The method of claim 15 wherein the exposing stepfurther comprises reducing the copper oxide according to the equation,Cu_(x)O+2H⁺=Cu+H₂O.
 17. The method of claim 15 wherein the exposing stepis carried out in a radio-frequency back sputter chamber.
 18. The methodof claim 14 further comprising determining a surface reflectivity of thecopper surface after the reducing step and controlling the reducing stepin response to the surface reflectivity.
 19. The method of claim 18wherein the step of determining a surface reflectivity comprises:determining a first surface reflectivity of the copper pad surface priorto the reducing step; determining a second surface reflectivity of thecopper pad surface following the reducing step; and controlling thereducing step according to the first and the second surfacereflectivity.
 20. A method for forming an aluminum layer on a copperpad, comprising: forming the copper pad, wherein unwanted copper oxideforms on the copper pad; reducing the copper oxide; and forming thealuminum layer on the reduced surface.
 21. The method of claim 20wherein the reducing step further comprises exposing the copper surfaceto hydrogen species ions.
 22. The method of claim 21 wherein theexposing step further comprises reducing the copper oxide according tothe equation, Cu_(x)O+2H⁺=Cu+H₂O.
 23. The method of claim 21 wherein theexposing step is carried out in a radio-frequency back sputter chamber.24. The method of claim 20 further comprising determining a surfacereflectivity of the copper surface after the reducing step andcontrolling the reducing step in response to the surface reflectivity.25. The method of claim 20 further comprising attaching a wire bond tothe aluminum layer.
 26. A method for removing oxide from a metalsurface, comprising: forming hydrogen species ions; and exposing theoxide to the hydrogen ions.
 27. A method for forming a bond pad in asubstrate of an integrated circuit, comprising: providing a firstconductive structure in the substrate; forming a plurality ofspaced-apart second conductive structures overlying the first conductivestructures; and forming the bond pad overlying the second conductivestructures.
 28. A solder bond structure comprising: a substrate; ahydrogen-reduced copper pad overlying the substrate; a passivation layeroverlying the copper pad and having an opening defined therein; anunder-bump metallization layer disposed within the opening; and whereinthe solder bond structure is disposed overlying the under-bumpmetaliization layer.
 29. The solder bond structure of claim 27 whereinthe copper pad comprises a bond pad for an integrated circuit, andwherein the substrate comprises doped semiconductor regions andinterconnect structures, and wherein the bond pad is in conductivecommunication with an interconnect structure, and wherein the solderbond structure comprises a solder bump.
 30. The solder bond structure ofclaim 27 wherein the copper pad comprises a bond pad for an integratedcircuit, and wherein the substrate comprises doped semiconductor regionsand interconnect structures, and wherein the bond pad is in conductivecommunication with an interconnect structure, and wherein the solderbond structure comprises an aluminum layer.
 31. The solder bondstructure of claim 27 wherein the copper pad comprises a bond pad for anintegrated circuit, and wherein the substrate comprises dopedsemiconductor regions and interconnect structures, and wherein the bondpad is in conductive communication with an interconnect structurethrough a plurality of spaced-apart conductive structures disposedbetween the interconnect structure and the copper pad.
 32. The solderbond structure of claim 31 wherein the plurality of spaced-apartconductive structures comprise a plurality of substantially verticalconductive vias.
 33. The solder bond structure of claim 31 wherein theplurality of spaced-apart conductive structures comprise a plurality ofcurrent-spreading conductive elements.
 34. The solder bond structure ofclaim 31 wherein the plurality of spaced-apart conductive structurescomprise a plurality of conductive trenches.
 35. A bond pad structure ina substrate of an integrated circuit, comprising: a substrate; a firstconductive structure disposed in the substrate; a plurality ofspaced-apart second conductive structures overlying the first conductivestructure; and a bond pad overlying the second conductive structures.36. The bond pad structure of claim 35 wherein the plurality ofspaced-apart second conductive structures comprise a plurality ofsubstantially vertical conductive vias.
 37. The bond pad structure ofclaim 35 wherein the plurality of spaced-apart second conductivestructures comprise a plurality of current-spreading conductiveelements.
 38. The bond pad structure of claim 35 wherein the pluralityof spaced-apart second conductive structures comprise a plurality ofconductive trenches.